Datasheet
Vinculum-II Embedded Dual USB Host Controller IC
Version 1.7
Document No.: FT_000138 Clearance No.: FTDI#143
Figure 6.3 - SPI CPOL CPHA Function
6.3 Serial Peripheral Interface – Slave
CLK
SS#
VNC2 - SPI Slave
External - SPI Master
MOSI
MISO
Figure 6.4 SPI Slave block diagram
VNC2 has two SPI Slave modules both of which use four wire interfaces: MOSI, MISO, CLK and SS#.
Their main purpose is to send data from main memory to the attached SPI master, and / or receive data
and send it to main memory. The SPI Slave is controlled by the internal CPU using internal memory
mapped I/O registers. It operates from the main system clock, although sampling of input data and
transmission of output data is controlled by the SPI clock (CLK). An SPI transfer can only be initiated by
the SPI Master and begins with the slave select signal being asserted. This is followed by a data byte
being clocked out with the master supplying CLK. The master always supplies the first byte, which is
called a command byte. After this the desired number of data bytes are transferred before the
transaction is terminated by the master de-asserting slave select. An SPI Master is able to abort a
transfer at any time by de-asserting its SS# output. This will cause the Slave to end its current transfer
and return to idle state.
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