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FT2232H_10 参数 Datasheet PDF下载

FT2232H_10图片预览
型号: FT2232H_10
PDF下载: 下载PDF文件 查看货源
内容描述: 双高速USB TO多用途UART / FIFO IC [DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC]
分类和应用: 先进先出芯片
文件页数/大小: 63 页 / 1469 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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Document No.: FT_000061  
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC  
Datasheet Version 2.09  
Clearance No.: FTDI#77  
3.4.5 FT2232H pins used in an MPSSE  
The FT2232H channel A and channel B each have a Multi-Protocol Synchronous Serial Engine (MPSSE).  
Each MPSSE can be independently configured to a number of industry standard serial interface protocols  
such as JTAG, I2C or SPI, or it can be used to implement a proprietary bus protocol. For example, it is  
possible to use one of the FT2232H‟s channels to connect to an SRAM configurable FPGA such as supplied  
by Altera or Xilinx. The FPGA device would normally be un-configured (i.e. have no defined function) at  
power-up. Application software on the PC could use the MPSSE to download configuration data to the  
FPGA over USB. This data would define the hardware function on power up. The other FT2232H channel  
would be available for another function. Alternatively each MPSSE can be used to control a number of  
GPIO pins. When configured in this mode, the pins used and the descriptions of the signals are shown  
Table 3.6  
Channel A  
Pin No.  
Channel B  
Pin No.  
Name  
Type  
MPSSE Configuration Description  
Clock Signal Output. For example:  
JTAG TCK, Test interface clock  
SPI SK, Serial Clock  
16  
17  
38  
39  
TCK/SK  
OUTPUT  
Serial Data Output. For example:  
JTAG TDI, Test Data Input  
SPI DO  
TDI/DO  
TDO/DI  
TMS/CS  
OUTPUT  
INPUT  
Serial Data Input. For example:  
JTAG TDO, Test Data output  
SPI DI, Serial Data Input  
18  
19  
40  
41  
Output Signal Select. For example:  
JTAG TMS, Test Mode Select  
SPI CS, Serial Chip Select  
OUTPUT  
21  
22  
23  
24  
26  
27  
28  
29  
30  
32  
33  
34  
43  
44  
45  
46  
48  
52  
53  
54  
55  
57  
58  
59  
GPIOL0  
GPIOL1  
GPIOL2  
GPIOL3  
GPIOH0  
GPIOH1  
GPIOH2  
GPIOH3  
GPIOH4  
GPIOH5  
GPIOH6  
GPIOH7  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
General Purpose input/output  
General Purpose input/output  
General Purpose input/output  
General Purpose input/output  
General Purpose input/output  
General Purpose input/output  
General Purpose input/output  
General Purpose input/output  
General Purpose input/output  
General Purpose input/output  
General Purpose input/output  
General Purpose input/output  
Table 3.8 Channel A and Channel B MPSSE Configured Pin Descriptions  
For a functional description of this mode, please refer to section 4.6 MPSSE Interface Mode Description.  
Copyright © 2010 Future Technology Devices International Limited  
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