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FT2232H_10 参数 Datasheet PDF下载

FT2232H_10图片预览
型号: FT2232H_10
PDF下载: 下载PDF文件 查看货源
内容描述: 双高速USB TO多用途UART / FIFO IC [DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC]
分类和应用: 先进先出芯片
文件页数/大小: 63 页 / 1469 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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Document No.: FT_000061  
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC  
Datasheet Version 2.09  
Clearance No.: FTDI#77  
3.4.8 FT2232H Pins Configured as a Host Bus Emulation Interface  
The FT2232H can be used to combine channel A and channel B to be configured as a host bus emulation  
interface mode which emulates a standard 8048 or 8051 MCU host.  
When configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.11  
Pin No.  
Name  
Type  
I/O  
Fast Serial Interface Configuration Description  
24,23,22,21,  
19,18,17,16  
ADBUS[7:0]  
Multiplexed bidirectional Address/Data bus AD7 to AD0  
OUTPUT  
34,33,32,30,  
29,28,27,26  
A[15:8]  
CS#  
Extended Address A15 to A8  
OUTPUT  
OUTPUT  
38  
39  
Active low chip select device during Read or Write.  
ALE  
Positive pulse to latch the address  
Active low read output.  
OUTPUT  
40  
41  
RD#  
WR#  
Active low write output. (Data is setup before WR# goes  
low, and is held after WR# goes high)  
OUTPUT  
INPUT  
Extends the time taken to perform a Read or Write  
operation if driven low. Pull up to VCORE if not being  
used.  
43  
44  
IORDY  
Master clock. Outputs the clock signal being used by the  
configured interface.  
CLKOUT  
OUTPUT  
I/O  
MPSSE mode instructions to set / clear or read the high  
byte of data can be used with this pin. Please refer to  
Application Note AN_108 for operation of these  
instructions.  
45  
I/O0  
I/O1  
I/O  
MPSSE mode instructions to set / clear or read the high  
byte of data can be used with this pin. In addition this  
pin has instructions which will make the controller wait  
until it is high, or wait until it is low. This can be used to  
connect to an IRQ pin of a peripheral chip. The FT2232H  
will wait for the interrupt, and then read the device, and  
pass the answer back to the host PC. I/O1 must be held  
in input mode if this option is used. Please refer to  
Application Note AN_108 for operation of these  
instructions.  
46  
Table 3.11 Channel A and Channel B Host Bus Emulation Interface Configured Pin Descriptions  
For a functional description of this mode, please refer to section 4.7 MCU Host Bus Emulation Mode  
Copyright © 2010 Future Technology Devices International Limited  
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