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FT2232H_10 参数 Datasheet PDF下载

FT2232H_10图片预览
型号: FT2232H_10
PDF下载: 下载PDF文件 查看货源
内容描述: 双高速USB TO多用途UART / FIFO IC [DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC]
分类和应用: 先进先出芯片
文件页数/大小: 63 页 / 1469 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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Document No.: FT_000061  
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC  
Datasheet Version 2.09  
Clearance No.: FTDI#77  
3.4.3 FT2232H pins used in an FT245 Style Asynchronous FIFO Interface  
The FT2232H channel A or channel B can be configured as a FT245 asynchronous FIFO interface. When  
configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.6. To  
enter this mode the external EEPROM must be set to make port A or B or both 245 mode. In this mode,  
data is written or read on the falling edge of the RD# or WR# signals.  
Channel A  
Pin No.  
Channel B  
Pin No.  
Name  
Type  
FT245 Configuration Description  
Channel A =  
24,23,22,21, 46,45,44,43, ADBUS[7:0]  
D7 to D0 bidirectional FIFO data. This bus is normally input  
unless RD# is low.  
I/O  
19,18,17,16  
41,40,39,38  
Channel B =  
BDBUS[7:0]  
When high, do not read data from the FIFO. When low,  
there is data available in the FIFO which can be read by  
driving RD# low. When RD# goes high again RXF# will  
26  
48  
RXF#  
TXE#  
OUTPUT always go high and only become low again if there is  
another byte to read. During reset this signal pin is tri-  
state, but pulled up to VCCIO via an internal 200kΩ  
resistor.  
When high, do not write data into the FIFO. When low, data  
can be written into the FIFO by strobing WR# high, then  
low. During reset this signal pin is tri-state, but pulled up to  
27  
52  
OUTPUT  
VCCIO via an internal 200kΩ resistor.  
Enables the current FIFO data byte to be driven onto  
D0...D7 when RD# goes low. Fetches the next FIFO data  
byte (if available) from the receive FIFO buffer when RD#  
goes high.  
28  
29  
53  
54  
RD#  
WR#  
INPUT  
Writes the data byte on the D0...D7 pins into the transmit  
FIFO buffer when WR# goes from high to low.  
INPUT  
The Send Immediate / WakeUp signal combines two  
functions on a single pin. If USB is in suspend mode  
(PWREN# = 1) and remote wakeup is enabled in the  
EEPROM , strobing this pin low will cause the device to  
request a resume on the USB Bus. Normally, this can be  
used to wake up the Host PC.  
30  
55  
SIWU  
INPUT  
During normal operation (PWREN# = 0), if this pin is  
strobed low any data in the device TX buffer will be sent out  
over USB on the next Bulk-IN request from the drivers  
regardless of the pending packet size. This can be used to  
optimize USB transfer speed for some applications. Tie this  
pin to VCCIO if not used. (Also see note 1, 2, 3 in section  
4.12)  
Table 3.6 Channel A and Channel B FT245 Style Asynchronous FIFO Configured Pin Descriptions  
Copyright © 2010 Future Technology Devices International Limited  
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