Document Revision History
Table 84. Document Revision History (continued)
Substantive Change(s)
Revision
Date
1
10/2007 • Adjusted maximum SYSCLK frequency down in Table 5, “SYSCLK AC Timing Specifications” per
device erratum GEN-13.
• Clarified notes to Table 6, “EC_GTX_CLK125 AC Timing Specifications.”
• Added Section 4.4, “PCI/PCI-X Reference Clock Timing.”
• Clarified descriptions and added PCI/PCI-X to Table 9, “PLL Lock Times.”
• Removed support for 266 and 200 Mbps data rates per device erratum GEN-13 in Section 6, “DDR and
DDR2 SDRAM.”
• Clarified Note 4 of Table 19, “DDR SDRAM Output AC Timing Specifications.”
• Clarified the reference clock used in Section 7.2, “DUART AC Electrical Specifications.”
• Corrected V (min) in Table 22, “GMII, MII, RMII, and TBI DC Electrical Characteristics.”
IH
• Corrected V (max) in Table 23, “GMII, MII, RMII, TBI, RGMII, RTBI, and FIFO DC Electrical
IL
Characteristics.”
• Removed DC parameters from Table 24, Table 25, Table 26, Table 27, Table 28, Table 29, Table 32,
Table 34, and Table 35.
• Corrected V (min) in Table 36, “MII Management DC Electrical Characteristics.”
IH
• Corrected t
(min) in Table 37, “MII Management AC Timing Specifications.”
MDC
• Updated parameter descriptions for t
, t
, t
, and t
in Table 40, “Local Bus
LBIVKH1 LBIVKH2 LBIXKH1
LBIXKH2
Timing Parameters (BV = 3.3 V)—PLL Enabled” and Table 40, “Local Bus Timing Parameters
DD
(BV = 2.5 V)—PLL Enabled.”
DD
• Updated parameter descriptions for t
, t
, t
, and t
in Table 42, “Local Bus
LBIVKH1 LBIVKL2 LBIXKH1
LBIXKL2
Timing Parameters—PLL Bypassed.” Note that t
and t
were previously labeled t
LBIVKL2
LBIXKL2 LBIVKH2
and t
.
LBIXKH2
• Added LUPWAIT signal to Figure 23, “Local Bus Signals (PLL Enabled)” and Figure 24, “Local Bus
Signals (PLL Bypass Mode).”
• Added LGTA signal to Figure 25, Figure 26, Figure 27 and Figure 28.
• Corrected LUPWAIT assertion in Figure 26 and Figure 28.
• Clarified the PCI reference clock in Section 14.2, “PCI/PCI-X AC Electrical Specifications”
• Added Section 17.1, “Package Parameters.”
• Added PBGA thermal information in Section 20.2, “Thermal for Version 2.1.1 and 2.1.2 Silicon
FC-PBGA with Full Lid.”
• Updated.”
• Updated Table 83, “Part Numbering Nomenclature.”
0
07/2007 • Initial Release
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
143
FREESCALE [ Freescale ]
