Document Revision History
Table 84. Document Revision History (continued)
Revision
1
Date
10/2007
Substantive Change(s)
• Adjusted maximum SYSCLK frequency down in
per
device erratum GEN-13.
• Clarified notes to
• Added
• Clarified descriptions and added PCI/PCI-X to
• Removed support for 266 and 200 Mbps data rates per device erratum GEN-13 in
• Clarified Note 4 of
• Clarified the reference clock used in
• Corrected V
IH
(min) in
• Corrected V
IL
(max) in
• Removed DC parameters from
and
• Corrected V
IH
(min) in
• Corrected t
MDC
(min) in
• Updated parameter descriptions for t
LBIVKH1
, t
LBIVKH2
, t
LBIXKH1
, and t
LBIXKH2
in
and
Table 40, “Local Bus Timing Parameters
(BV
DD
= 2.5 V)—PLL Enabled.”
• Updated parameter descriptions for t
LBIVKH1
, t
LBIVKL2
, t
LBIXKH1
, and t
LBIXKL2
in
Note that t
LBIVKL2
and t
LBIXKL2
were previously labeled t
LBIVKH2
and t
LBIXKH2
.
• Added LUPWAIT signal to
and
• Added LGTA signal to
and
• Corrected LUPWAIT assertion in
and
• Clarified the PCI reference clock in
• Added
Section 17.1, “Package Parameters.”
• Added PBGA thermal information in
• Updated.”
• Updated
• Initial Release
0
07/2007
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
143
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
