Document Revision History
Table 84. Document Revision History (continued)
Revision
3
Date
01/2009
Substantive Change(s)
• [Section
4.6, “Platform Frequency Requirements for PCI-Express and Serial RapidIO.”
Changed
minimum frequency equation to be 527 MHz for PCI x8.
• In
added note 7.
•
Changed platform clock frequency to 4.2.
•
Added MII after GMII
and add ‘or 2.5 V’ after 3.3 V.
• In
modified table title to include GMII, MII, RMII, and TBI.
• In
and
changed clock period minimum to 5.3.
• In
added a note.
• In
and
removed subtitle from table title.
• In
and
changed all instances of PMA to TSECn.
• In
Replaced first paragraph.
• In
and
changed all instances of REF_CLK to
TSEC
n_TX_CLK.
• In
changed all instances of OV
DD
to LV
DD
/TV
DD
.
• In
high from 32 to 48 ns.
• Added new section,
•
Section 16.1, “DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK.”
Added new
paragraph.
•
Section 17.1, “DC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK.”
Added new
paragraph.
• Added information to
Figure 63,
both in figure and in note.
•
Modified the recommendation.
•
In Silicon Version column added Ver. 2.1.2.
•
•
•
•
•
Removed 1:1 support on
Removed MDM from
MDM is an Output.
(AVDD_PLAT).
(AVDD_CORE).
Split
(formerly called just “PLL Power
Supply Filter Circuit”) into three figures: the original (now specific for AVDD_PCI/AVDD_LBIU) and two
new ones.
2
04/2008
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
142
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
