Document Revision History
23 Document Revision History
provides a revision history for the MPC8548E hardware specification.
Table 84. Document Revision History
Revision
6
Date
12/2009
Substantive Change(s)
• In
added explanation that Power-On Ramp Rate is required to
avoid falsely triggering ESD circuitry.
• In
changed required ramp rate from 545 V/s for MVREF and VDD/XVDD/SVDD to 3500 V/s
for MVREF and 4000 V/s for VDD.
• In
deleted ramp rate requirement for XVDD/SVDD.
• In
footnote 1 changed voltage range of concern from 0–400 mV to 20–500mV.
• In
added footnote 2 explaining that VDD voltage ramp rate is intended to control ramp rate of
AVDD pins.
• In
35/75 for RX_CLK duty cycle.
• Updated tMDKHDX in
• Added a reference to Revision 2.1.2.
• Updated
Table 55, “MII
• Added
• In
,” and in
moved text, “MII management voltage” from LV
DD
/TV
DD
to OV
DD
, added “Ethernet management” to
OVDD row of input voltage section.
• In
time.
• In
DD
/OV
DD
to
OV
DD
.
• Modified
to reflect that there is only one SerDes.
• Modified DDR clk rate min from 133 to 166 MHz.
• Modified note in
• In
column, and changed all instances of “LO” to “L0.” In addition, added note 8.
• In
and in note 3, changed “TRX-EYE-MEDIAN-to-MAX-JITTER,” to “T
RX-EYE-MEDIAN-to-MAX-JITTER
.”
• Modified
• Added a note on
to limit the SYSCLK to 100 MHz if the core
frequency is less than 1200 MHz
• In
• Added note to
5
10/2009
4
04/2009
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
141
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
