High-Speed Serial Interfaces (HSSI)
occurs in the 1-15MHz range. The source impedance of the clock driver should be 50 ohms to match the
transmission line and reduce reflections which are a source of noise to the system.
Table 59 describes some AC parameters common to SGMII, PCI Express and Serial RapidIO protocols.
Table 59. SerDes Reference Clock Common AC Parameters
At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.1V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Rising Edge Rate
Falling Edge Rate
Rise Edge Rate
Fall Edge Rate
1.0
1.0
+200
—
4.0
4.0
V/ns
V/ns
mV
mV
%
2, 3
2, 3
2
Differential Input High Voltage
Differential Input Low Voltage
V
IH
V
-200
20
2
IL
Rising edge rate (SDn_REF_CLK) to falling edge rate
(SDn_REF_CLK) matching
Rise-Fall
Matching
—
1, 4
Notes:
1. Measurment taken from single ended waveform.
2. Measurment taken from differential waveform.
3. Measured from -200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered
on the differential zero crossing. See Figure 52.
4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a 200
mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The median cross
point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate
of SDn_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference should not
exceed 20% of the slowest edge rate. See Figure 53.
V
= +200 mV
0.0 V
IH
V
= -200 mV
IL
SDn_REF_CLK
minus
SDn_REF_CLK
Figure 52. Differential Measurement Points for Rise and Fall Time
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
80
Freescale Semiconductor
FREESCALE [ Freescale ]
