High-Speed Serial Interfaces (HSSI)
clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular
clock driver chip.
LVPECL CLK
Driver Chip
MPC8572E
50 Ω
SDn_REF_CLK
CLK_Out
10nF
R2
SerDes Refer.
CLK Receiver
R1
R1
100 Ω differential PWB trace
10nF
Clock Driver
R2
SDn_REF_CLK
CLK_Out
50 Ω
Figure 50. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
Figure 51 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with MPC8572E SerDes reference clock
input’s DC requirement.
Single-Ended
CLK Driver Chip
MPC8572E
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
50 Ω
SDn_REF_CLK
33 Ω
Clock Driver
CLK_Out
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
SDn_REF_CLK
50 Ω
50 Ω
Figure 51. Single-Ended Connection (Reference Only)
15.2.4 AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100KHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15MHz is filtered by the PLL. The most problematic phase noise
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
79
FREESCALE [ Freescale ]
