High-Speed Serial Interfaces (HSSI)
NOTE
Figure 48 to Figure 51 below are for conceptual reference only. Due to the
fact that clock driver chip's internal structure, output impedance and
termination requirements are different between various clock driver chip
manufacturers, it is very possible that the clock circuit reference designs
provided by clock driver chip vendor are different from what is shown
below. They might also vary from one vendor to the other. Therefore,
Freescale Semiconductor can neither provide the optimal clock driver
reference circuits, nor guarantee the correctness of the following clock
driver connection reference circuits. The system designer is recommended
to contact the selected clock driver chip vendor for the optimal reference
circuits with the MPC8572E SerDes reference clock receiver requirement
provided in this document.
Figure 48 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It
assumes that the DC levels of the clock driver chip is compatible with MPC8572E SerDes reference clock
input’s DC requirement.
MPC8572E
HCSL CLK Driver Chip
50 Ω
SDn_REF_CLK
CLK_Out
33 Ω
33 Ω
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
Clock Driver
CLK_Out
SDn_REF_CLK
50 Ω
Clock driver vendor dependent
source termination resistor
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
Figure 48. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
77
FREESCALE [ Freescale ]
