Overview
— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs.
— Interrupt summary registers allow fast identification of interrupt source.
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Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec,
IKE, SSL/TLS, SRTP, 802.16e, and 3GPP
— Four crypto-channels, each supporting multi-command descriptor chains
– Dynamic assignment of crypto-execution units through an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
— PKEU—public key execution unit
– RSA and Diffie-Hellman; programmable field size up to 4096 bits
– Elliptic curve cryptography with F m and F(p) modes and programmable field size up to
2
1023 bits
— DEU—Data Encryption Standard execution unit
– DES, 3DES
– Two key (K1, K2, K1) or three key (K1, K2, K3)
– ECB, CBC and OFB-64 modes for both DES and 3DES
— AESU—Advanced Encryption Standard unit
– Implements the Rijndael symmetric key cipher
– ECB, CBC, CTR, CCM, GCM, CMAC, OFB-128, CFB-128, and LRW modes
– 128-, 192-, and 256-bit key lengths
— AFEU—ARC four execution unit
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— MDEU—message digest execution unit
– SHA-1 with 160-bit message digest
– SHA-2 (SHA-256, SHA-384, SHA-512)
– MD5 with 128-bit message digest
– HMAC with all algorithms
— KEU—Kasumi execution unit
– Implements F8 algorithm for encryption and F9 algorithm for integrity checking
– Also supports A5/3 and GEA-3 algorithms
— RNG—random number generator
— XOR engine for parity checking in RAID storage applications
— CRC execution unit
– CRC-32 and CRC-32C
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Pattern Matching Engine with DEFLATE decompression
— Regular expression (regex) pattern matching
– Built-in case insensitivity, wildcard support, no pattern explosion
– Cross-packet pattern detection
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
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Freescale Semiconductor
FREESCALE [ Freescale ]
