Freescale Semiconductor
Technical Data
Document Number: MPC8572EEC
Rev. 4, 06/2010
MPC8572E PowerQUICC III
Integrated Processor
Hardware Specifications
Contents
1 Overview
This section provides a high-level overview of the features
of the MPC8572E processor. Figure 1 shows the major
functional units within the MPC8572E.
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 10
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15
4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18
6. DDR2 and DDR3 SDRAM Controller . . . . . . . . . . . 19
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8. Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 28
1.1
Key Features
9. Ethernet Management Interface
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 50
The following list provides an overview of the MPC8572E
feature set:
10. Local Bus Controller (eLBC) . . . . . . . . . . . . . . . . . . 53
11. Programmable Interrupt Controller . . . . . . . . . . . . . 65
12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
15. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 71
16. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
17. Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
18. Package Description . . . . . . . . . . . . . . . . . . . . . . . . 100
19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
21. System Design Information . . . . . . . . . . . . . . . . . . 125
22. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 135
23. Document Revision History . . . . . . . . . . . . . . . . . . 137
•
Two high-performance 32-bit Book E–enhanced
cores that implement the Power Architecture®
technology:
— Each core is identical to the core within the
MPC8548 processor.
— 32-Kbyte L1 instruction cache and 32-Kbyte L1
data cache with parity protection. Caches can be
locked entirely or on a per-line basis, with
separate locking for instructions and data.
— Signal-processing engine (SPE) APU (auxiliary
processing unit). Provides an extensive
instruction set for vector (64-bit) integer and
fractional operations. These instructions use both
© 2010 Freescale Semiconductor, Inc. All rights reserved.
FREESCALE [ Freescale ]
