Overview
2.0 dual-role controller, a programmable interrupt controller, dual I
2
C controllers, a 4-channel DMA
controller, an enhanced secured digital host controller, and a general-purpose I/O port. The block diagram
of the MPC8378E is shown in
MPC8378E
DUART
Dual I
2
C
Timers
GPIO
SPI
Interrupt
Controller
e300 Core
32-Kbyte
D-Cache
32-Kbyte
I-Cache
DDR1/DDR2
SDRAM
Controller
Security
Enhanced
Local Bus
USB 2.0
Hi-Speed
DMA
PCI
Host
Device
eTSEC
SGMII,
RGMII, RMII,
RTBI, MII
eTSEC
SGMII,
RGMII, RMII,
RTBI, MII
PCI
Express
x1
PCI
Express
x1
Figure 1. MPC8378E Block Diagram and Features
The following features are supported in the MPC8378E:
• e300c4s core built on Power Architecture™ technology with 32-Kbyte instruction cache and
32-Kbyte data cache, a floating point unit, and two integer units
• DDR1/DDR2 memory controller supporting a 32/64-bit interface
• Peripheral interfaces, such as a 32-bit PCI interface with up to 66-MHz operation
• 32-bit local bus interface running up to 133-MHz
• USB 2.0 (full/high speed) support
• Power management controller for low-power consumption
• High degree of software compatibility with previous-generation PowerQUICC processor-based
designs for backward compatibility and easier software migration
• Optional security engine provides acceleration for control and data plane security protocols
The optional security engine (SEC 3.0) is noted with the extension “E” at the end. It allows CPU-intensive
cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator
provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms.
MPC8378E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2
2
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
