Package and Pin Listings
Table 56. MPC8347EA (PBGA) Pinout Listing (continued)
Power
Notes
Signal
Package Pin Number
Pin Type
Supply
MRAS
AF7
O
O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
3
MCAS
AG6
AE7, AH7, AH4, AF2
AG23, AH23
MCS[0:3]
MCKE[0:1]
MCK[0:5]
MCK[0:5]
MODT[0:3]
MBA[2]
O
O
AH15, AE24, AE2, AF14, AE23, AD3
AG15, AD23, AE3, AG14, AF24, AD2
AG5, AD4, AH6, AF4
AD22
O
—
—
—
—
9
O
O
O
MDIC0
AG11
I/O
I/O
MDIC1
AF12
—
9
Local Bus Controller Interface
LAD[0:31]
T4, T5, T1, R2, R3, T2, R1, R4, P1, P2,
P3, P4, N1, N4, N2, N3, M1, M2, M3,
N5, M4, L1, L2, L3, K1, M5, K2, K3, J1,
J2, L5, J3
I/O
OVDD
—
LDP[0]/CKSTOP_OUT
LDP[1]/CKSTOP_IN
LDP[2]/LCS[4]
H1
I/O
I/O
I/O
I/O
O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
12
—
—
—
—
—
K5
H2
LDP[3]/LCS[5]
G1
LA[27:31]
J4, H3, G2, F1, G3
LCS[0:3]
J5, H4, F2, E1
O
LWE[0:3]/LSDDQM[0:3]/LBS[0:3]
LBCTL
F3, G4, D1, E2
O
H5
E3
O
LALE
O
LGPL0/LSDA10/cfg_reset_source0
LGPL1/LSDWE/cfg_reset_source1
LGPL2/LSDRAS/LOE
LGPL3/LSDCAS/cfg_reset_source2
LGPL4/LGTA/LUPWAIT/LPBSE
LGPL5/cfg_clkin_div
LCKE
F4
I/O
I/O
O
D2
C1
C2
I/O
I/O
I/O
O
C3
B3
E4
LCLK[0:2]
D4, A3, C4
U3
O
LSYNC_OUT
O
LSYNC_IN
Y2
I
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
69
FREESCALE [ Freescale ]
