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MPC8347ECVVAGDB 参数 Datasheet PDF下载

MPC8347ECVVAGDB图片预览
型号: MPC8347ECVVAGDB
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8347EA的PowerQUICC II Pro整合型主机处理器的硬件规格 [MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications]
分类和应用: 外围集成电路PC时钟
文件页数/大小: 99 页 / 727 K
品牌: FREESCALE [ Freescale ]
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PCI  
1
Table 45. PCI AC Timing Specifications at 66 MHz (continued)  
Parameter  
Symbol2  
Min  
Max  
Unit  
Notes  
3, 5  
Input hold from clock  
tPCIXKH  
0
ns  
Notes:  
1. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to the PCI chapter of the reference manual for a  
description of M66EN.  
2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs  
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with  
respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going  
to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went  
high (H) relative to the frame signal (F) going to the valid (V) state.  
3. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.  
4. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the  
component pin is less than or equal to the leakage current specification.  
5. Input timings are measured at the pin.  
Table 46 provides the PCI AC timing specifications at 33 MHz.  
Table 46. PCI AC Timing Specifications at 33 MHz  
Parameter  
Symbol1  
Min  
Max  
Unit  
Notes  
Clock to output valid  
t
2
11  
14  
ns  
ns  
ns  
ns  
ns  
2
PCKHOV  
Output hold from clock  
Clock to output high impedance  
Input setup to clock  
Input hold from clock  
Notes:  
tPCKHOX  
tPCKHOZ  
tPCIVKH  
tPCIXKH  
2
3.0  
0
2, 3  
2, 4  
2, 4  
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs  
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with  
respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going  
to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went  
high (H) relative to the frame signal (F) going to the valid (V) state.  
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.  
3. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the  
component pin is less than or equal to the leakage current specification.  
4. Input timings are measured at the pin.  
Figure 34 provides the AC test load for PCI.  
OVDD/2  
Output  
Z0 = 50 Ω  
RL = 50 Ω  
Figure 34. PCI AC Test Load  
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12  
Freescale Semiconductor  
49