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MPC8347ECVVAGDB 参数 Datasheet PDF下载

MPC8347ECVVAGDB图片预览
型号: MPC8347ECVVAGDB
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8347EA的PowerQUICC II Pro整合型主机处理器的硬件规格 [MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications]
分类和应用: 外围集成电路PC时钟
文件页数/大小: 99 页 / 727 K
品牌: FREESCALE [ Freescale ]
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I2C  
12 I2C  
2
This section describes the DC and AC electrical characteristics for the I C interface of the MPC8347EA.  
2
12.1 I C DC Electrical Characteristics  
2
Table 42 provides the DC electrical characteristics for the I C interface of the MPC8347EA.  
2
Table 42. I C DC Electrical Characteristics  
At recommended operating conditions with OVDD of 3.3 V 10%.  
Parameter  
Symbol  
Min  
Max  
Unit  
Notes  
Input high voltage level  
Input low voltage level  
Low level output voltage  
VIH  
VIL  
0.7 × OVDD  
OVDD + 0.3  
0.3 × OVDD  
0.2 × OVDD  
250  
V
V
1
–0.3  
0
VOL  
V
Output fall time from VIH(min) to VIL(max) with a bus  
capacitance from 10 to 400 pF  
tI2KLKV  
20 + 0.1 × CB  
ns  
2
Pulse width of spikes which must be suppressed by the  
input filter  
tI2KHKL  
0
50  
10  
10  
ns  
μA  
pF  
3
4
Input current each I/O pin (input voltage is between  
0.1 × OVDD and 0.9 × OVDD(max)  
II  
–10  
Capacitance for each I/O pin  
CI  
Notes:  
1. Output voltage (open drain or open collector) condition = 3 mA sink current.  
2. CB = capacitance of one bus line in pF.  
3. Refer to the MPC8349EA Integrated Host Processor Family Reference Manual, for information on the digital filter used.  
4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.  
2
12.2 I C AC Electrical Specifications  
2
Table 43 provides the AC timing parameters for the I C interface of the MPC8347EA. Note that all values  
refer to V (min) and V (max) levels (see Table 42).  
IH  
IL  
2
Table 43. I C AC Electrical Specifications  
Parameter  
Symbol1  
Min  
Max  
Unit  
SCL clock frequency  
fI2C  
tI2CL  
0
400  
kHz  
μs  
Low period of the SCL clock  
1.3  
0.6  
0.6  
0.6  
High period of the SCL clock  
tI2CH  
μs  
Setup time for a repeated START condition  
tI2SVKH  
tI2SXKL  
μs  
Hold time (repeated) START condition (after this period, the first clock  
pulse is generated)  
μs  
Data setup time  
tI2DVKH  
tI2DXKL  
100  
ns  
Data hold time:CBUS compatible masters  
I2C bus devices  
02  
μs  
0.93  
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12  
Freescale Semiconductor  
46