Peripheral operating requirements and behaviors
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
6.6.1 ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications.
6.6.1.1 12-bit ADC operating conditions
Table 19. 12-bit ADC operating conditions
Symbol Description
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
VDDA
ΔVDDA
ΔVSSA
VREFH
Supply voltage
Supply voltage
Ground voltage
Absolute
—
Delta to VDD (VDD-VDDA
)
0
+100
+100
VDDA
mV
mV
V
2
2
3
Delta to VSS (VSS - VSSA
)
0
ADC reference
voltage high
VDDA
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
3
VADIN
CADIN
Input voltage
VREFL
—
—
4
VREFH
5
V
Input capacitance
• 8-/10-/12-bit modes
pF
RADIN
RAS
Input resistance
—
2
5
kΩ
Analog source
resistance
12-bit modes
fADCK < 4 MHz
4
—
—
—
5
kΩ
fADCK
Crate
ADC conversion ≤ 12-bit mode
clock frequency
1.0
18.0
MHz
5
6
ADC conversion ≤ 12 bit modes
rate
No ADC hardware averaging
20.000
—
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
VSSA
.
4. This resistance is external to MCU. The analog source resistance must be kept as low as possible to achieve the best
results. The results in this data sheet were derived from a system which has < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1ns.
5. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool
KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Freescale Semiconductor, Inc.
31
FREESCALE [ Freescale ]
