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MK60DN256ZVLQ10 参数 Datasheet PDF下载

MK60DN256ZVLQ10图片预览
型号: MK60DN256ZVLQ10
PDF下载: 下载PDF文件 查看货源
内容描述: K60次系列数据手册 [K60 Sub-Family Data Sheet]
分类和应用: 外围集成电路微控制器时钟
文件页数/大小: 79 页 / 2005 K
品牌: FREESCALE [ Freescale ]
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General  
Table 6. Power consumption operating behaviors (continued)  
Symbol Description  
Min.  
Typ.  
Max.  
Unit  
Notes  
IDD_VBAT Average current when CPU is not accessing  
RTC registers  
10  
• @ 1.8V  
• @ –40 to 25°C  
• @ 70°C  
0.71  
1.01  
2.82  
0.81  
1.3  
μA  
μA  
μA  
• @ 105°C  
• @ 3.0V  
4.3  
• @ –40 to 25°C  
• @ 70°C  
0.84  
1.17  
3.16  
0.94  
1.5  
μA  
μA  
μA  
• @ 105°C  
4.6  
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See  
each module's specification for its supply current.  
2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode.  
All peripheral clocks disabled.  
3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All  
peripheral clocks enabled.  
4. Max values are measured with CPU executing DSP instructions.  
5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode.  
6. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks  
disabled. Code executing from flash.  
7. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks  
enabled but peripherals are not in active operation. Code executing from flash.  
8. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks  
disabled.  
9. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA.  
10. Includes 32kHz oscillator current and RTC operation.  
5.2.5.1 Diagram: Typical IDD_RUN operating behavior  
The following data was measured under these conditions:  
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater  
than 50 MHz frequencies  
• USB regulator disabled  
• No GPIOs toggled  
• Code execution from flash with cache enabled  
• For the ALLOFF curve, all peripheral clocks are disabled except FTFL  
K60 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.  
18  
Freescale Semiconductor, Inc.  
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