Freescale Semiconductor, Inc.
LIST OF ILLUSTRATIONS
Figure
Title
Page
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
3-1
3-2
4-1
4-2
4-3
4-4
5-1
5-2
5-3
5-4
5-5
7-1
7-2
7-3
7-4
8-1
8-2
9-1
9-2
9-3
10-1
10-2
10-3
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-10
MC68HC11F1 Block Diagram ........................................................................ 1-2
Pin Assignments for MC68HC11F1 68-Pin PLCC ......................................... 2-1
Pin Assignments for MC68HC11F1 80-Pin QFP ............................................ 2-2
External Reset Circuit ..................................................................................... 2-3
Common Crystal Connections ........................................................................ 2-4
External Oscillator Connections ..................................................................... 2-4
One Crystal Driving Two MCUs ..................................................................... 2-4
4XOUT Signal Driving a Second MCU ........................................................... 2-5
Programming Model ....................................................................................... 3-2
Stacking Operations ....................................................................................... 3-4
MC68HC11F1 Memory Map .......................................................................... 4-3
RAM Standby MODB/V
Connections ..................................................... 4-4
STBY
Address Map for I/O and Program Chip Selects .......................................... 4-19
Address Map for General-Purpose Chip Select ........................................... 4-20
Processing Flow Out of Reset (1 of 2) ......................................................... 5-12
Processing Flow Out of Reset (2 of 2) ......................................................... 5-13
Interrupt Priority Resolution (1 of 2) ............................................................. 5-14
Interrupt Priority Resolution (2 of 2) ............................................................. 5-15
Interrupt Source Resolution Within SCI ........................................................ 5-16
SCI Transmitter Block Diagram ...................................................................... 7-2
SCI Receiver Block Diagram .......................................................................... 7-3
SCI Baud Rate Generator Block Diagram .................................................... 7-10
Interrupt Source Resolution Within SCI ........................................................ 7-12
SPI Block Diagram ......................................................................................... 8-2
SPI Transfer Format ....................................................................................... 8-3
Timer Clock Divider Chains ............................................................................ 9-2
Capture/Compare Block Diagram .................................................................. 9-4
Pulse Accumulator ....................................................................................... 9-16
A/D Converter Block Diagram ...................................................................... 10-2
Electrical Model of an A/D Input Pin (Sample Mode) ................................... 10-3
A/D Conversion Sequence ........................................................................... 10-4
Test Methods ..................................................................................................A-4
Timer Inputs ...................................................................................................A-5
POR External Reset Timing Diagram .............................................................A-6
STOP Recovery Timing Diagram ...................................................................A-7
WAIT Recovery from Interrupt Timing Diagram .............................................A-8
Interrupt Timing Diagram ................................................................................A-9
Port Read Timing Diagram ...........................................................................A-10
Port Write Timing Diagram ...........................................................................A-10
Expansion Bus Timing ..................................................................................A-13
SPI Master Timing (CPHA = 0) ....................................................................A-15
TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
