Freescale Semiconductor, Inc.
SS
(INPUT)
SS IS HELD HIGH ON MASTER
1
13
13
12
12
5
4
SCK (CPOL = 0)
(OUTPUT)
SEE
NOTE
4
5
SCK (CPOL = 1)
(OUTPUT)
SEE
NOTE
6
7
MISO
(INPUT)
MSB IN
BIT 6 - - - -1
11
LSB IN
11 (ref)
10
BIT 6 - - - -1
10 (ref)
MOSI
(OUTPUT)
MASTER MSB OUT
13
MASTER LSB OUT
12
NOTE: This first clock edge is generated internally but is not seen at the SCK pin.
Figure A-10 SPI Master Timing (CPHA = 0)
SS
(INPUT)
SS IS HELD HIGH ON MASTER
1
13
12
13
5
SCK (CPOL = 0)
(OUTPUT)
SEE
NOTE
4
5
SCK (CPOL = 1)
(OUTPUT)
SEE
NOTE
4
12
6
7
MISO
(INPUT)
MSB IN
BIT 6 - - - -1
11
LSB IN
11 (ref)
10
BIT 6 - - - -1
10 (ref)
MOSI
(OUTPUT)
MASTER MSB OUT
13
MASTER LSB OUT
12
NOTE: This last clock edge is generated internally but is not seen at the SCK pin.
Figure A-11 SPI Master Timing (CPHA = 1)
ELECTRICAL CHARACTERISTICS
TECHNICAL DATA
A-15
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