Table 5. Pin Functions by Primary and Alternate Purpose
Drive
Primary
Function
SecondaryF
unction
Tertiary
Quaternary
Function
Wired OR
Control
Pull-up/
Pin on
Pin on
Pin on
Pin Group
Strength/
Function
Pull-down2 144 MAPBGA 144 LQFP 100 LQFP
Control1
ADC
AN[7:0]
—
—
PAN[7:0]
N/A
—
—
K9–K12; L9,
L12; M9–M10
74–77;
66–69
43–46;
51–54
VDDA
VSSA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
High
High
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
—
—
—
—
—
—
—
—
—
—
—
—
—
L11
M12
L10
M11
C12
D12
C11
D11
D1
73
70
50
47
49
48
73
72
74
71
7
—
VRH
—
72
VRL
—
71
Clock
Generation
EXTAL
—
106
105
107
104
33
XTAL
—
VDDPLL
VSSPLL
RTC_EXTAL
RTC_XTAL
ALLPST
DDATA[3:0]
—
—
—
RTC
—
E1
34
8
Debug
Data
—
L3
42
30
—
PDD[7:4]
—
F10–F11; G9;
H10
83–86
PST[3:0]
FEC_COL
—
—
—
—
—
—
—
—
—
—
PDD[3:0]
PTI0
High
Low
Low
Low
Low
—
—
F9; G10–G12
87–90
109
—
76
75
87
FEC
B11
B12
B8
FEC_CRS
PTI1
108
FEC_RXCLK
FEC_RXD[0:3]
PTI2
120
PTI[3:6]
A8; B7; C7; D7 122–123;
126–127
89–90;
93–94
FEC_RXDV
FEC_RXER
—
—
—
—
—
—
—
—
PTI7
PTJ0
Low
Low
Low
Low
C8
A9
B9
121
119
88
86
FEC_TXCLK
FEC_TXD[0:3]
PTJ1
117
84
PTJ[2:5]
A11; B10; C9;
D9
113–110
77–80
FREESCALE [ Freescale ]
