Table 4. Pin Functions by Primary and Alternate Purpose (continued)
Drive
Pin
Group
Primary
Function
Secondary
Function
Tertiary
Quaternary
Function
Slew Rate / Pull-up /
Pin on
Pin on 81
MAPBGA LQFP/QFN
Pin on 64
Strength /
Function
Control1 Pull-down2 100 LQFP
Control1
QSPI
QSPI_DIN/
EZPD
URXD1
UTXD1
URTS1
GPIO
GPIO
GPIO
PDSR[2]
PDSR[1]
PDSR[3]
PSRR[2]
PSRR[1]
PSRR[3]
—
—
16
17
18
F3
G1
G2
12
13
14
QSPI_DOUT/
EZPQ
QSPI_CLK/
EZPCK
SCL
pull-up7
QSPI_CS3
QSPI_CS2
QSPI_CS1
QSPI_CS0
RSTI
SYNCA
GPIO
GPIO
GPIO
GPIO
—
PDSR[7]
PDSR[6]
PDSR[5]
PDSR[4]
N/A
PSRR[7]
PSRR[6]
PSRR[5]
PSRR[4]
N/A
12
13
19
20
96
97
5
F1
F2
H2
H1
A3
B3
C2
—
—
—
15
59
60
3
—
—
—
SDA
—
—
pull-up7
pull-up8
—
UCTS1
—
Reset8
RSTO
—
—
—
high
FAST
Test
TEST
—
—
—
N/A
N/A
pull-down
pull-up9
pull-up9
pull-up9
pull-up9
—
Timers, 16-bit
GPT3
—
PWM7
PWM5
PWM3
PWM1
PWM6
PWM4
PWM2
PWM0
—
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PDSR[23] PSRR[23]
PDSR[22] PSRR[22]
PDSR[21] PSRR[21]
PDSR[20] PSRR[20]
PDSR[19] PSRR[19]
PDSR[18] PSRR[18]
PDSR[17] PSRR[17]
PDSR[16] PSRR[16]
PDSR[11] PSRR[11]
PDSR[10] PSRR[10]
GPT2
—
GPT1
—
GPT0
—
Timers, 32-bit
DTIN3
DTOUT3
DTOUT2
DTOUT1
DTOUT0
32
31
37
36
6
H3
J3
19
18
23
22
4
DTIN2
—
DTIN1
—
G4
H4
C1
D3
D1
D2
DTIN0
—
UART 0
UCTS0
URTS0
URXD0
UTXD0
—
—
—
9
7
—
PDSR[9]
PDSR[8]
PSRR[9]
PSRR[8]
—
7
5
—
—
8
6
FREESCALE [ Freescale ]
