Detailed Register Address Map
MSCAN Foreground Receive and Transmit Buffer Layout
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
W
R
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
0xXX1E CANxTTSRH
0xXX1F CANxTTSRL
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
W
0x0180-023F Reserved
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
0
0
0
0
0
0
0
0
0x0180-
0x023F
Reserved
W
0x0240 -0x027F Port Integration Module (PIM) Map 4 of 4
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
W
R
0x0240
PTT
PTT7
PTT6
PTT5
PTT4
PTT3
PTT2
PTT1
PTT0
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
0x0241
0x0242
0x0243
0x0244
0x0245
0x0246
0x0247
PTIT
DDRT
W
R
DDRT7
RDRT7
PERT7
DDRT6
RDRT6
PERT6
DDRT5
RDRT5
PERT5
DDRT4
RDRT4
PERT4
DDRT3
RDRT3
PERT3
DDRT2
RDRT2
PERT2
DDRT1
RDRT1
PERT1
DDRT0
RDRT0
PERT0
W
R
RDRT
W
R
PERT
W
R
PPST
PPST7
0
PPST6
0
PPST5
0
PPST4
0
PPST3
0
PPST2
0
PPST1
0
PPST0
0
W
R
Reserved
PTTRR
W
R
0
PTTRR7
PTTRR6
PTTRR5
PTTRR4
PTTRR2
PTTRR1
PTTRR0
W
S12P-Family Reference Manual, Rev. 1.13
560
Freescale Semiconductor
FREESCALE [ Freescale ]
