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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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128 KByte Flash Module (S12FTMRC128K1V1)  
How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from  
BUSCLK for Flash program and erase command operations  
The command write sequence used to set Flash command parameters and launch execution  
Valid Flash commands available for execution  
13.4.3.1 Writing the FCLKDIV Register  
Prior to issuing any Flash program or erase command after a reset, the user is required to write the  
FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz. Table 13-7 shows recommended  
values for the FDIV field based on BUSCLK frequency.  
NOTE  
Programming or erasing the Flash memory cannot be performed if the bus  
clock runs at less than 0.8 MHz. Setting FDIV too high can destroy the Flash  
memory due to overstress. Setting FDIV too low can result in incomplete  
programming or erasure of the Flash memory cells.  
When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the  
FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written,  
any Flash program or erase command loaded during a command write sequence will not execute and the  
ACCERR bit in the FSTAT register will set.  
13.4.3.2 Command Write Sequence  
The Memory Controller will launch all valid Flash commands entered using a command write sequence.  
Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see  
Section 13.3.2.7) and the CCIF flag should be tested to determine the status of the current command write  
sequence. If CCIF is 0, the previous command write sequence is still active, a new command write  
sequence cannot be started, and all writes to the FCCOB register are ignored.  
CAUTION  
Writes to any Flash register must be avoided while a Flash command is  
active (CCIF=0) to prevent corruption of Flash register contents and  
Memory Controller behavior.  
13.4.3.2.1  
Define FCCOB Contents  
The FCCOB parameter fields must be loaded with all required parameters for the Flash command being  
executed. Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX  
register (see Section 13.3.2.3).  
The contents of the FCCOB parameter fields are transferred to the Memory Controller when the user clears  
the CCIF command completion flag in the FSTAT register (writing 1 clears the CCIF to 0). The CCIF flag  
will remain clear until the Flash command has completed. Upon completion, the Memory Controller will  
return CCIF to 1 and the FCCOB register will be used to communicate any results. The flow for a generic  
command write sequence is shown in Figure 13-26.  
S12P-Family Reference Manual, Rev. 1.13  
Freescale Semiconductor  
451  
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