128 KByte Flash Module (S12FTMRC128K1V1)
Offset Module Base + 0x000E
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-20. Flash Reserved3 Register (FRSV3)
All bits in the FRSV3 register read 0 and are not writable.
13.3.2.15 Flash Reserved4 Register (FRSV4)
This Flash register is reserved for factory testing.
Offset Module Base + 0x000F
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-21. Flash Reserved4 Register (FRSV4)
All bits in the FRSV4 register read 0 and are not writable.
13.3.2.16 Flash Option Register (FOPT)
The FOPT register is the Flash option register.
Offset Module Base + 0x0010
7
6
5
4
3
2
1
0
R
W
NV[7:0]
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 13-22. Flash Option Register (FOPT)
All bits in the FOPT register are readable but are not writable.
During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash
configuration field at global address 0x3_FF0E located in P-Flash memory (see Table 13-3) as indicated
by reset condition F in Figure 13-22. If a double bit fault is detected while reading the P-Flash phrase
containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set.
S12P-Family Reference Manual, Rev. 1.13
448
Freescale Semiconductor
FREESCALE [ Freescale ]
