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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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Serial Communication Interface (S12SCIV5)  
NOTE  
In single-wire operation data from the TXD pin is inverted if RXPOL is set.  
11.4.8 Loop Operation  
In loop operation the transmitter output goes to the receiver input. The RXD pin is disconnected from the  
SCI.  
Transmitter  
TXD  
Receiver  
RXD  
Figure 11-31. Loop Operation (LOOPS = 1, RSRC = 0)  
Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1  
(SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Clearing the RSRC  
bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled  
(TE = 1 and RE = 1).  
NOTE  
In loop operation data from the transmitter is not recognized by the receiver  
if RXPOL and TXPOL are not the same.  
11.5 Initialization/Application Information  
11.5.1 Reset Initialization  
See Section 11.3.2, “Register Descriptions”.  
11.5.2 Modes of Operation  
11.5.2.1 Run Mode  
Normal mode of operation.  
To initialize a SCI transmission, see Section 11.4.5.2, “Character Transmission”.  
11.5.2.2 Wait Mode  
SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1  
(SCICR1).  
If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode.  
If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation  
state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver  
enable bit, RE, or the transmitter enable bit, TE.  
S12P-Family Reference Manual, Rev. 1.13  
Freescale Semiconductor  
395  
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