Device Overview MC9S12P-Family
Figure 1-5. MC9S12P-Family 48 QFN pinout
VDDA/VRH
PAD07/AN07
PWM3/KWP3/PP3
PWM2/KWP2/PP2
PWM1/KWP1/PP1
PWM0/IOC0/PT0
IOC1/PT1
36
35
34
1
2
3
4
5
6
7
8
9
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
PAD09/AN09
PAD08/AN08
PE0/XIRQ
MC9S12P-Family 33
32
48 QFN
IOC2/PT2
IOC3/PT3
PWM4/IOC4/PT4
API_EXTCLK/PWM5/IOC5/PT5
IOC6/PT6
31
30
29
28
27
26
25
10
11
12
IOC7/PT7
MODC/BKGD
1.7.2
Pin Assignment Overview
Table 1-6 provides a summary of which Ports are available for each package option. Routing of pin
functions is summarized in Table 1-7.
Table 1-6. Port Availability by Package Option
Port
80 QFP
64 LQFP
48 QFN
Port AD/ADC Channels
10/10
10/10
10/10
Port A pins
8
8
8
5
6
7
4
4
4
4
3
6
6
4
0
0
4
1
6
3
2
Port B pins
Port E pins inc. IRQ/XIRQ input only
Port J
Port M
Port P
Port S
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
31
FREESCALE [ Freescale ]
