Freescale’s Scalable Controller Area Network (S12MSCANV3)
— a) the 14 most significant bits of the extended identifier plus the SRR and IDE bits of CAN 2.0B
messages or
— b) the 11 bits of the standard identifier, the RTR and IDE bits of CAN 2.0A/B messages.
Figure 8-41 shows how the first 32-bit filter bank (CANIDAR0–CANIDA3,
CANIDMR0–3CANIDMR) produces filter 0 and 1 hits. Similarly, the second filter bank
(CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces filter 2 and 3 hits.
•
•
Eight identifier acceptance filters, each to be applied to the first 8 bits of the identifier. This mode
implements eight independent filters for the first 8 bits of a CAN 2.0A/B compliant standard
identifier or a CAN 2.0B compliant extended identifier. Figure 8-42 shows how the first 32-bit filter
bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces filter 0 to 3 hits. Similarly,
the second filter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces filter 4 to
7 hits.
Closed filter. No CAN message is copied into the foreground buffer RxFG, and the RXF flag is
never set.
CAN 2.0B
Extended Identifier
ID28
ID10
IDR0
IDR0
ID21 ID20
ID3 ID2
IDR1
IDR1
ID15 ID14
IDR2
IDR2
ID7 ID6
IDR3
IDR3
RTR
ID3
CAN 2.0A/B
Standard Identifier
IDE
ID10
ID3 ID10
AM7
AC7
CANIDMR0
CANIDAR0
AM0 AM7
AC0 AC7
CANIDMR1
CANIDAR1
AM0 AM7
AC0 AC7
CANIDMR2
CANIDAR2
AM0 AM7
AC0 AC7
CANIDMR3
CANIDAR3
AM0
AC0
ID Accepted (Filter 0 Hit)
Figure 8-40. 32-bit Maskable Identifier Acceptance Filter
S12P-Family Reference Manual, Rev. 1.13
290
Freescale Semiconductor
FREESCALE [ Freescale ]
