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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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Freescale’s Scalable Controller Area Network (S12MSCANV3)  
Table 8-18. CANIDAC Register Field Descriptions  
Field  
Description  
5-4  
Identifier Acceptance Mode — The CPU sets these flags to define the identifier acceptance filter organization  
IDAM[1:0] (see Section 8.4.3, “Identifier Acceptance Filter”). Table 8-19 summarizes the different settings. In filter closed  
mode, no message is accepted such that the foreground buffer is never reloaded.  
2-0  
Identifier Acceptance Hit Indicator — The MSCAN sets these flags to indicate an identifier acceptance hit (see  
IDHIT[2:0] Section 8.4.3, “Identifier Acceptance Filter”). Table 8-20 summarizes the different settings.  
Table 8-19. Identifier Acceptance Mode Settings  
IDAM1  
IDAM0  
Identifier Acceptance Mode  
0
0
1
1
0
1
0
1
Two 32-bit acceptance filters  
Four 16-bit acceptance filters  
Eight 8-bit acceptance filters  
Filter closed  
Table 8-20. Identifier Acceptance Hit Indication  
IDHIT2  
IDHIT1  
IDHIT0  
Identifier Acceptance Hit  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Filter 0 hit  
Filter 1 hit  
Filter 2 hit  
Filter 3 hit  
Filter 4 hit  
Filter 5 hit  
Filter 6 hit  
Filter 7 hit  
The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a  
message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.  
8.3.2.13 MSCAN Reserved Register  
This register is reserved for factory testing of the MSCAN module and is not available in normal system  
operating modes.  
S12P-Family Reference Manual, Rev. 1.13  
270  
Freescale Semiconductor  
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