S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2.16 Autonomous Periodical Interrupt Trimming Register (CPMUAPITR)
The CPMUAPITR register configures the trimming of the API time-out period.
0x02F3
7
6
5
4
3
2
1
0
R
W
0
0
APITR5
APITR4
APITR3
APITR2
APITR1
APITR0
Reset
F
F
F
F
F
F
0
0
After de-assert of System Reset a value is automatically loaded from the Flash memory.
Figure 7-20. Autonomous Periodical Interrupt Trimming Register (CPMUAPITR)
Read: Anytime
Write: Anytime
Table 7-16. CPMUAPITR Field Descriptions
Description
Field
7–2
Autonomous Periodical Interrupt Period Trimming Bits — See Table 7-17 for trimming effects. The
APITR[5:0] APITR[5:0] value represents a signed number influencing the ACLK period time.
Table 7-17. Trimming Effect of APITR
Bit
Trimming Effect
APITR[5]
APITR[4]
APITR[3]
APITR[2]
APITR[1]
APITR[0]
Increases period
Decreases period less than APITR[5] increased it
Decreases period less than APITR[4]
Decreases period less than APITR[3]
Decreases period less than APITR[2]
Decreases period less than APITR[1]
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
225
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