S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2.17 Autonomous Periodical Interrupt Rate High and Low Register
(CPMUAPIRH / CPMUAPIRL)
The CPMUAPIRH and CPMUAPIRL registers allow the configuration of the autonomous periodical
interrupt rate.
0x02F4
7
6
5
4
3
2
1
0
R
W
APIR15
APIR14
APIR13
APIR12
APIR11
APIR10
APIR9
APIR8
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-21. Autonomous Periodical Interrupt Rate High Register (CPMUAPIRH)
0x02F5
7
6
5
4
3
2
1
0
R
W
APIR7
APIR6
APIR5
APIR4
APIR3
APIR2
APIR1
APIR0
Reset
0
0
0
0
0
0
0
0
Figure 7-22. Autonomous Periodical Interrupt Rate Low Register (CPMUAPIRL)
Read: Anytime
Write: If APIFE=0, then write anytime, else writes have no effect.
Table 7-18. CPMUAPIRH / CPMUAPIRL Field Descriptions
Field
Description
Autonomous Periodical Interrupt Rate Bits — These bits define the time-out period of the API. See
15-0
APIR[15:0] Table 7-19 for details of the effect of the autonomous periodical interrupt rate bits.
The period can be calculated as follows depending on logical value of the APICLK bit:
APICLK=0: Period = 2*(APIR[15:0] + 1) * f
ACLK
APICLK=1: Period = 2*(APIR[15:0] + 1) * Bus Clock period
S12P-Family Reference Manual, Rev. 1.13
226
Freescale Semiconductor
FREESCALE [ Freescale ]
