Device Overview MC9S12P-Family
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Pulse width modulation (PWM) module with 6 x 8-bit channels
10-channel, 12-bit resolution successive approximation analog-to-digital converter (ATD)
One serial peripheral interface (SPI) module
One serial communication interface (SCI) module supporting LIN communications
One multi-scalable controller area network (MSCAN) module (supporting CAN protocol 2.0A/B)
On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages
Autonomous periodic interrupt (API)
1.3
Module Features
The following sections provide more details of the modules implemented on the MC9S12P family.
1.3.1
S12 16-Bit Central Processor Unit (CPU)
S12 CPU is a high-speed 16-bit processing unit:
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Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution
Includes many single-byte instructions. This allows much more efficient use of ROM space.
Extensive set of indexed addressing capabilities, including:
— Using the stack pointer as an indexing register in all indexed operations
— Using the program counter as an indexing register in all but auto increment/decrement mode
— Accumulator offsets using A, B, or D accumulators
— Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8)
1.3.2
On-Chip Flash with ECC
On-chip flash memory on the MC9S12P features the following:
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Up to 128 Kbyte of program flash memory
— 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction
and double fault detection
— Erase sector size 512 bytes
— Automated program and erase algorithm
— User margin level setting for reads
— Protection scheme to prevent accidental program or erase
4 Kbyte data flash space
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— 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction
and double fault detection
— Erase sector size 256 bytes
— Automated program and erase algorithm
— User margin level setting for reads
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
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