Device Overview MC9S12P-Family
1.2.1
MC9S12P Family Comparison
Table 1 provides a summary of different members of the MC9S12P family and their proposed features.
This information is intended to provide an understanding of the range of functionality offered by this
microcontroller family.
Table 1. MC9S12P Family
Feature
MC9S12P32
MC9S12P64
MC9S12P96
MC9S12P128
CPU
CPU12-V1
4 Kbytes
Flash memory (ECC)
32 Kbytes
2 Kbytes
64 Kbytes
4 Kbytes
96 Kbytes
128 Kbytes
Data flash (ECC)
RAM
6 Kbytes
MSCAN
1
SCI
1
SPI
1
Timer
8 ch x 16-bit
6 ch x 8-bit
PWM
ADC
10 ch x 12-bit
Frequency modulated PLL
Yes
Yes
External oscillator
(4 – 16 MHz Pierce with
loop control)
Internal 1 MHz RC
oscillator
Yes
Supply voltage
Execution speed
Package
3.15 V – 5.5 V
Static(1) – 32 MHz
80 QFP, 64 LQFP, 48 QFN
1. P or D Flash erasing or programming requires a minimum bus frequency of 1MHz
1.2.2
Chip-Level Features
On-chip modules available within the family include the following features:
•
•
•
•
•
•
•
•
S12 CPU core
Up to 128 Kbyte on-chip flash with ECC
4 Kbyte data flash with ECC
Up to 6 Kbyte on-chip SRAM
Phase locked loop (IPLL) frequency multiplier with internal filter
4–16 MHz amplitude controlled Pierce oscillator
1 MHz internal RC oscillator
Timer module (TIM) supporting input/output channels that provide a range of 16-bit input capture,
output compare, counter, and pulse accumulator functions
S12P-Family Reference Manual, Rev. 1.13
18
Freescale Semiconductor
FREESCALE [ Freescale ]
