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MC9S08QE8 参数 Datasheet PDF下载

MC9S08QE8图片预览
型号: MC9S08QE8
PDF下载: 下载PDF文件 查看货源
内容描述: 8位HCS08中央处理器 [8-Bit HCS08 Central Processor Unit]
分类和应用:
文件页数/大小: 46 页 / 942 K
品牌: FREESCALE [ Freescale ]
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Electrical Characteristics  
) (continued)  
Table 16. 12-bit ADC Characteristics (V  
= V  
, V  
= V  
REFH  
DDAD REFL SSAD  
C
Characteristic  
Conditions  
12 bit mode  
Symbol  
Min.  
Typical1  
Max.  
Unit  
Comment  
±2  
±4  
Input Leakage  
Error  
Pad leakage4  
*RAS  
D
10 bit mode  
8 bit mode  
EIL  
±0.2  
LSB2  
±0.1  
±1.2  
–40°C to 25°C  
25°C to 85°C  
1.646  
1.769  
Temp Sensor  
Slope  
D
D
m
mV/°C  
Temp Sensor  
Voltage  
25°C  
VTEMP25  
701.2  
mV  
1
Typical values assume VDDAD = 3.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for  
reference only and are not tested in production.  
2
3
4
1 LSB = (VREFH – VREFL)/2N  
Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes  
Based on input pad leakage current. Refer to pad electricals.  
3.13 Flash Specifications  
This section provides details about program/erase times and program-erase endurance for the flash memory.  
Program and erase operations do not require any special power sources other than the normal V supply. For more detailed  
DD  
information about program/erase operations, see the Memory section.  
Table 17. Flash Characteristics  
C
Characteristic  
Symbol  
Min  
Typical  
Max  
Unit  
Supply voltage for program/erase  
–40°C to 85°C  
D
Vprog/erase  
VRead  
fFCLK  
1.8  
1.8  
150  
5
3.6  
3.6  
V
D
D
D
P
P
P
P
Supply voltage for read operation  
Internal FCLK frequency1  
Internal FCLK period (1/FCLK)  
Byte program time (random location)2  
Byte program time (burst mode)2  
Page erase time2  
Mass erase time2  
Byte program current3  
Page erase current3  
V
200  
6.67  
kHz  
μs  
tFcyc  
tprog  
9
tFcyc  
tFcyc  
tFcyc  
tFcyc  
mA  
mA  
tBurst  
4
4000  
20,000  
4
tPage  
tMass  
RIDDBP  
RIDDPE  
6
Program/erase endurance4  
TL to TH = –40°C to + 85°C  
T = 25°C  
C
C
10,000  
15  
100,000  
cycles  
years  
Data retention5  
tD_ret  
100  
1
2
The frequency of this clock is controlled by a software setting.  
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied  
for calculating approximate time to program and erase.  
MC9S08QE8 Series, Rev. 3  
Freescale Semiconductor  
Preliminary  
27  
Subject to Change Without Notice  
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