Development Support
Monitor ROM (MON)
VDD
RST
PA7
4096 + 32 CGMXCLK CYCLES
24 BUS CYCLES
256 BUS CYCLES (MINIMUM)
FROM HOST
PA0
1
1
3
1
3
2
1
FROM MCU
NOTES:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
3 = Wait 1 bit time before sending next byte.
Figure 18-13. Monitor Mode Entry Timing
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA
Data Sheet
287
Development Support