Monitor ROM
Addr.
Register Name
Bit 7
6
IF21
R
5
IF20
R
4
IF19
R
3
IF18
R
2
IF17
R
1
Bit 0
Read:
Write:
Reset:
Read:
0
R
0
IF16
R
IF15
R
Interrupt Status Register 3
(INT3)
$FE06
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D
$FE0E
Reserved Write:
Reset:
Read:
0
0
0
0
HVEN
MASS
ERASE
PGM
FLASH Control Register
(FLCR)
Write:
Reset:
Read:
0
BPR7
0
0
BPR6
0
0
BPR5
0
0
BPR4
0
0
BPR3
0
0
BPR2
0
0
BPR1
0
0
BPR0
0
FLASH Block Protect
Register Write:
(FLBPR)
Reset:
Read:
Reserved Write:
Reset:
R
R
R
R
R
R
R
R
Read:
R
R
R
R
R
R
R
R
Reserved Write:
Reset:
Read:
Break Address
Register High Write:
Bit 15
0
14
13
0
12
0
11
0
10
0
9
0
1
Bit 8
0
(BRKH)
Reset:
0
Read:
Break Address
Register Low Write:
Bit 7
0
6
0
5
4
3
2
Bit 0
(BRKL)
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
Reset:
Break Status and Control
BRKE
0
BRKA
Register Read:
(BRKSCR)
Write:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset: LVIOUT
$FE0F LVI Status Register (LVISR) Read:
Write:
0
0
0
0
0
0
0
0
Read:
OSCSEL1 OSCSEL0
R
R
R
R
R
R
Mask Option Register
(MOR)#
$FFCF
Write:
Erased:
Reset:
1
1
1
1
1
1
1
1
U
U
U
U
U
U
U
U
Read:
Write:
Reset:
Low byte of reset vector
COP Control Register
(COPCTL)
$FFFF
Writing clears COP counter (any value)
Unaffected by reset
# MOR is a non-volatile FLASH register; write by programming.
U = Unaffected X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 9)
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
39
FREESCALE [ Freescale ]
