Memory
Addr.
Register Name
Bit 7
ADx
R
6
ADx
R
5
ADx
R
4
ADx
R
3
ADx
R
2
ADx
R
1
ADx
R
Bit 0
ADx
R
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
ADC Data Register Low 0
(ADRL0)
$005A
0
0
0
0
0
0
0
0
AD9
R
AD8
R
AD7
R
AD6
R
AD5
R
AD4
R
AD3
R
AD2
R
ADC Data Register Low 1
(ADRL1)
$005B
$005C
0
0
0
0
0
0
0
0
AD9
R
AD8
R
AD7
R
AD6
R
AD5
R
AD4
R
AD3
R
AD2
R
ADC Data Register Low 2
(ADRL2)
0
0
0
0
0
0
0
0
AD9
R
AD8
R
AD7
R
AD6
R
AD5
R
AD4
R
AD3
R
AD2
R
ADC Data Register Low 3
(ADRL3)
$005D
0
0
0
0
0
0
0
0
ADC Auto-scan Control
AUTO1
0
AUTO0
0
ASCAN
0
$005E
$005F
Register Write:
(ADASCR)
Reset:
0
0
0
0
0
Read:
Unimplemented Write:
Reset:
Read:
SBSW
Note
0
R
R
R
R
R
R
R
0
SIM Break Status Register
(SBSR)
$FE00
Write:
Reset:
Note: Writing a logic 0 clears SBSW.
Read:
Write:
Reset:
Read:
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
SIM Reset Status Register
(SRSR)
$FE01
1
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
$FE02
$FE03
$FE04
$FE05
Reserved Write:
Reset:
Read:
SIM Break Flag Control Reg-
BCFE
R
R
R
R
R
R
R
ister Write:
(SBFCR)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
IF6
R
IF5
R
IF4
R
IF3
R
IF2
R
IF1
R
0
0
R
Interrupt Status Register 1
(INT1)
R
0
0
0
0
0
0
0
0
IF14
R
IF13
R
IF12
R
IF11
R
IF10
R
IF9
R
IF8
IF7
R
Interrupt Status Register 2
(INT2)
R
0
0
0
0
0
0
0
0
U = Unaffected
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 9)
MC68HC908AP Family Data Sheet, Rev. 4
38
Freescale Semiconductor
FREESCALE [ Freescale ]
