Monitor ROM
Addr.
Register Name
Bit 7
6
5
4
3
2
0
1
Bit 0
Read:
0
0
0
0
KEYF
Keyboard Status and Control
IMASK
0
MODE
$001A
Register Write:
(KBSCR)
Reset:
ACK
0
0
0
KBIE6
0
0
0
0
0
Read:
Keyboard Interrupt
Enable Register Write:
KBIE7
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
0
KBIE0
$001B
$001C
$001D
(KBIER)
Reset:
0
0
0
0
0
0
0
0
0
Read:
IRQ2F
0
ACK2
0
IRQ2 Status and Control Reg-
PUC0ENB
IMASK2
MODE2
ister Write:
(INTSCR2)
Reset:
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
0
STOP_
ICLKDIS
STOP_ STOP_
RCLKEN XCLKEN
OSCCLK1 OSCCLK0
SCIBDSRC
0
Configuration Register 2
(CONFIG2)†
0
0
0
0
0
0
0
0
0
0
0
0
IRQ1F
0
0
0
† One-time writable register after each reset.
Read:
0
ACK1
0
IRQ1 Status and Control Reg-
ister Write:
IMASK1
MODE1
$001E
(INTSCR1)
Reset:
Read:
Write:
Reset:
0
COPRS
0
0
STOP
0
0
COPD
0
LVISTOP LVIRSTD LVIPWRD LVIREGD
SSREC
0
Configuration Register 1
(CONFIG1)†
$001F
0
0
0
0
0
† One-time writable register after each reset.
Read:
TOF
0
0
TRST
0
Timer 1 Status and
Control Register Write:
TOIE
TSTOP
PS2
PS1
PS0
$0020
$0021
$0022
$0023
$0024
$0025
(T1SC)
Reset:
0
0
1
0
0
0
9
0
Read:
Bit 15
14
13
12
11
10
Bit 8
Timer 1 Counter
Register High Write:
(T1CNTH)
Reset:
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Read:
Bit 7
Bit 0
Timer 1 Counter
Register Low Write:
(T1CNTL)
Reset:
0
Bit 15
1
0
0
0
0
0
0
0
Read:
Timer 1 Counter Modulo Reg-
14
13
12
11
10
9
Bit 8
ister High Write:
(T1MODH)
Reset:
1
1
1
1
1
1
1
1
Read:
Timer 1 Counter Modulo
Bit 7
6
5
4
3
2
1
Bit 0
Register Low Write:
(T1MODL)
Reset:
1
CH0F
0
1
CH0IE
0
1
MS0B
0
1
MS0A
0
1
ELS0B
0
1
1
CH0MAX
0
Read:
ELS0A
TOV0
Timer 1 Channel 0 Status and
Control Register (T1SC0)
Write:
Reset:
0
0
0
U = Unaffected
X = Indeterminate
= Unimplemented
R
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 9)
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
33
FREESCALE [ Freescale ]
