3V SPI Characteristics
SS
INPUT
3
1
SPSCK INPUT
CPOL = 0
5
4
4
5
2
SPSCK INPUT
CPOL = 1
9
8
MISO
INPUT
SLAVE MSB OUT
BITS 6–1
BITS 6–1
SLAVE LSB OUT
11
NOTE
11
6
7
10
MOSI
OUTPUT
MSB IN
LSB IN
Note: Not defined but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS
INPUT
1
SPSCK INPUT
CPOL = 0
5
4
5
2
3
SPSCK INPUT
CPOL = 1
4
10
9
SLAVE LSB OUT
8
MISO
OUTPUT
NOTE
SLAVE MSB OUT
BITS 6–1
BITS 6–1
11
6
7
10
MOSI
INPUT
MSB IN
LSB IN
Note: Not defined but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 22-4. SPI Slave Timing
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
313
FREESCALE [ Freescale ]
