Electrical Specifications
22.15 5V SPI Characteristics
Table 22-15. SPI Characteristics (5V)
Diagram
Number(1)
Characteristic(2)
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
f
OP/2
fOP
fOP/128
dc
MHz
MHz
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
tCYC
tCYC
1
2
1
128
—
tLead(S)
tLag(S)
tCYC
tCYC
2
3
Enable lead time
Enable lag time
1
1
—
—
Clock (SPSCK) high time
Master
Slave
tSCKH(M)
tSCKH(S)
tCYC –25
1/2 tCYC –25
64 tCYC
—
4
5
6
7
ns
ns
Clock (SPSCK) low time
Master
Slave
tSCKL(M)
tSCKL(S)
tCYC –25
1/2 tCYC –25
64 tCYC
—
ns
ns
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
30
30
—
—
ns
ns
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
30
30
—
—
ns
ns
Access time, slave(3)
CPHA = 0
CPHA = 1
tA(CP0)
tA(CP1)
8
9
0
0
40
40
ns
ns
Disable time, slave(4)
tDIS(S)
—
40
ns
Data valid time, after enable edge
Master
Slave(5)
tV(M)
tV(S)
10
—
—
50
50
ns
ns
Data hold time, outputs, after enable edge
Master
Slave
tHO(M)
tHO(S)
11
0
0
—
—
ns
ns
1. Numbers refer to dimensions in Figure 22-3 and Figure 22-4.
2. All timing is shown with respect to 20% V and 70% V , unless noted; 100 pF load on all SPI pins.
DD
DD
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
5. With 100 pF on all SPI pins
MC68HC908AP Family Data Sheet, Rev. 4
310
Freescale Semiconductor
FREESCALE [ Freescale ]
