Serial Peripheral Interface Module (SPI)
13.12.5 CGND (Clock Ground)
CGND is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. It
is internally connected to V as shown in Table 13-1.
SS
13.13 I/O Registers
Three registers control and monitor SPI operation:
•
•
•
SPI control register (SPCR)
SPI status and control register (SPSCR)
SPI data register (SPDR)
13.13.1 SPI Control Register
•
•
•
•
•
Enables SPI module interrupt requests
Configures the SPI module as master or slave
Selects serial clock polarity and phase
Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
Enables the SPI module
Address:
$0010
Bit 7
6
R
0
5
SPMSTR
1
4
CPOL
0
3
2
1
SPE
0
Bit 0
SPTIE
0
Read:
Write:
Reset:
SPRIE
0
CPHA
SPWOM
1
0
= Unimplemented
= Reserved
R
Figure 13-13. SPI Control Register (SPCR)
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR
bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See
Figure 13-4 and Figure 13-6.) To transmit data between SPI modules, the SPI modules must have
identical CPOL values. Reset clears the CPOL bit.
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial clock and SPI data. (See
Figure 13-4 and Figure 13-6.) To transmit data between SPI modules, the SPI modules must have
identical CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1
between bytes. (See Figure 13-12.) Reset sets the CPHA bit.
MC68HC908AP Family Data Sheet, Rev. 4
224
Freescale Semiconductor
FREESCALE [ Freescale ]
