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MC908AP32CFAE 参数 Datasheet PDF下载

MC908AP32CFAE图片预览
型号: MC908AP32CFAE
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内容描述: [MC908AP32CFAE]
分类和应用:
文件页数/大小: 325 页 / 4102 K
品牌: FREESCALE [ Freescale ]
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I/O Signals  
13.12.4 SS (Slave Select)  
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a  
slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission.  
(See 13.5 Transmission Formats.) Since it is used to indicate the start of a transmission, the SS must be  
toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low  
between transmissions for the CPHA = 1 format. See Figure 13-12.  
MISO/MOSI  
MASTER SS  
BYTE 1  
BYTE 2  
BYTE 3  
SLAVE SS  
CPHA = 0  
SLAVE SS  
CPHA = 1  
Figure 13-12. CPHA/SS Timing  
When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as  
a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can  
still prevent the state of the SS from creating a MODF error. (See 13.13.2 SPI Status and Control  
Register.)  
NOTE  
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a  
high-impedance state. The slave SPI ignores all incoming SPSCK clocks,  
even if it was already in the middle of a transmission.  
When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to  
prevent multiple masters from driving MOSI and SPSCK. (See 13.7.2 Mode Fault Error.) For the state of  
the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit  
is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data  
direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless  
of the state of the data direction register of the shared I/O port.  
The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and  
reading the port data register. (See Table 13-3.)  
Table 13-3. SPI Configuration  
SPE  
SPMSTR  
MODFEN  
SPI Configuration  
Not enabled  
State of SS Logic  
General-purpose I/O;  
SS ignored by SPI  
X(1)  
0
0
1
1
1
X
X
0
Slave  
Input-only to SPI  
General-purpose I/O;  
SS ignored by SPI  
1
Master without MODF  
Master with MODF  
1
1
Input-only to SPI  
Note 1. X = Don’t care  
MC68HC908AP Family Data Sheet, Rev. 4  
Freescale Semiconductor  
223  
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