Serial Peripheral Interface Module (SPI)
Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the transmit
data register in break mode does not initiate a transmission nor is this data transferred into the shift
register. Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect.
13.12 I/O Signals
The SPI module has five I/O pins and shares four of them with a parallel I/O port. They are:
•
•
•
•
•
MISO — Data received
MOSI — Data transmitted
SPSCK — Serial clock
SS — Slave select
CGND — Clock ground (internally connected to V )
SS
2
The SPI has limited inter-integrated circuit (I C) capability (requiring software support) as a master in a
2
single-master environment. To communicate with I C peripherals, MOSI becomes an open-drain output
2
when the SPWOM bit in the SPI control register is set. In I C communication, the MOSI and MISO pins
2
are connected to a bidirectional pin from the I C peripheral and through a pullup resistor to V
.
DD
13.12.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmits serial data. In full duplex operation, the MISO pin
of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI
simultaneously receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is
configured as a slave when its SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a
multiple-slave system, a logic 1 on the SS pin puts the MISO pin in a high-impedance state.
When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction
register of the shared I/O port.
13.12.2 MOSI (Master Out/Slave In)
MOSI is one of the two SPI module pins that transmits serial data. In full-duplex operation, the MOSI pin
of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI
simultaneously transmits data from its MOSI pin and receives data on its MISO pin.
When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction
register of the shared I/O port.
13.12.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and slave devices. In a master MCU,
the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex
operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles.
When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data
direction register of the shared I/O port.
MC68HC908AP Family Data Sheet, Rev. 4
222
Freescale Semiconductor
FREESCALE [ Freescale ]
