Infrared Serial Communications Interface Module (IRSCI)
RPF — Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit
search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start
bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. Polling
RPF before disabling the SCI module or entering stop mode can show whether a reception is in
progress.
1 = Reception in progress
0 = No reception in progress
12.9.6 IRSCI Data Register
The IRSCI data register is the buffer between the internal data bus and the receive and transmit shift
registers. Reset has no effect on data in the IRSCI data register.
Address:
$0045
Bit 7
R7
6
5
4
3
2
1
Bit 0
R0
Read:
Write:
Reset:
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
T7
T0
Unaffected by reset
Figure 12-18. IRSCI Data Register (IRSCDR)
R7/T7–R0/T0 — Receive/Transmit Data Bits
Reading the IRSCDR accesses the read-only received data bits, R7–R0. Writing to the IRSCDR writes
the data to be transmitted, T7–T0. Reset has no effect on the IRSCDR.
NOTE
Do not use read/modify/write instructions on the IRSCI data register.
12.9.7 IRSCI Baud Rate Register
The baud rate register selects the baud rate for both the receiver and the transmitter.
Address:
$0046
Bit 7
6
0
5
SCP1
0
4
SCP0
0
3
2
1
SCR1
0
Bit 0
SCR0
0
Read:
Write:
Reset:
CKS
0
R
SCR2
0
0
0
= Unimplemented
R
= Reserved
Figure 12-19. IRSCI Baud Rate Register (IRSCBR)
CKS — Baud Clock Input Select
This read/write bit selects the source clock for the baud rate generator. Reset clears the CKS bit,
selecting CGMXCLK.
1 = Bus clock drives the baud rate generator
0 = CGMXCLK drives the baud rate generator
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown in Table 12-7. Reset clears SCP1
and SCP0.
MC68HC908AP Family Data Sheet, Rev. 4
206
Freescale Semiconductor
FREESCALE [ Freescale ]
