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MC908AP32CFAE 参数 Datasheet PDF下载

MC908AP32CFAE图片预览
型号: MC908AP32CFAE
PDF下载: 下载PDF文件 查看货源
内容描述: [MC908AP32CFAE]
分类和应用:
文件页数/大小: 325 页 / 4102 K
品牌: FREESCALE [ Freescale ]
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Infrared Serial Communications Interface Module (IRSCI)  
it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit.  
Also, after the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle  
condition can set the IDLE bit. Reset clears the IDLE bit.  
1 = Receiver input idle  
0 = Receiver input active (or idle since the IDLE bit was cleared)  
OR — Receiver Overrun Bit  
This clearable, read-only bit is set when software fails to read the IRSCDR before the receive shift  
register receives the next character. The OR bit generates an SCI error CPU interrupt request if the  
ORIE bit in IRSCC3 is also set. The data in the shift register is lost, but the data already in the IRSCDR  
is not affected. Clear the OR bit by reading IRSCS1 with OR set and then reading the IRSCDR. Reset  
clears the OR bit.  
1 = Receive shift register full and SCRF = 1  
0 = No receiver overrun  
Software latency may allow an overrun to occur between reads of IRSCS1 and IRSCDR in the  
flag-clearing sequence. Figure 12-16 shows the normal flag-clearing sequence and an example of an  
overrun caused by a delayed flag-clearing sequence. The delayed read of IRSCDR does not clear the  
OR bit because OR was not set when IRSCS1 was read. Byte 2 caused the overrun and is lost. The  
next flag-clearing sequence reads byte 3 in the IRSCDR instead of byte 2.  
In applications that are subject to software latency or in which it is important to know which byte is lost  
due to an overrun, the flag-clearing routine can check the OR bit in a second read of IRSCS1 after  
reading the data register.  
NORMAL FLAG CLEARING SEQUENCE  
BYTE 1  
BYTE 2  
BYTE 3  
BYTE 4  
READ IRSCS1  
SCRF = 1  
OR = 0  
READ IRSCS1  
SCRF = 1  
OR = 0  
READ IRSCS1  
SCRF = 1  
OR = 0  
READ IRSCDR  
BYTE 1  
READ IRSCDR  
BYTE 2  
READ IRSCDR  
BYTE 3  
DELAYED FLAG CLEARING SEQUENCE  
BYTE 1  
BYTE 2  
BYTE 3  
BYTE 4  
READ IRSCS1  
SCRF = 1  
OR = 0  
READ IRSCS1  
SCRF = 1  
OR = 1  
READ IRSCDR  
BYTE 1  
READ IRSCDR  
BYTE 3  
Figure 12-16. Flag Clearing Sequence  
MC68HC908AP Family Data Sheet, Rev. 4  
204  
Freescale Semiconductor  
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