Timebase Register Description
TBR[2:0] — Timebase Rate Selection
These read/write bits are used to select the rate of timebase interrupts as shown in Table 10-1.
NOTE
Do not change TBR[2:0] bits while the timebase is enabled (TBON = 1).
Table 10-1. Timebase Rate Selection for OSCCLK = 32.768-kHz
Timebase Interrupt Rate
TBR2
TBR1
TBR0
Divider
Hz
0.125
0.25
0.5
ms
8000
4000
2000
1000
~2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
262144
131072
65536
32768
64
1
512
32
1024
2048
4096
~1
16
~0.5
~0.24
8
TACK — Timebase ACKnowledge
The TACK bit is a write-only bit and always reads as 0. Writing a logic 1 to this bit clears TBIF, the
timebase interrupt flag bit. Writing a logic 0 to this bit has no effect.
1 = Clear timebase interrupt flag
0 = No effect
TBIE — Timebase Interrupt Enabled
This read/write bit enables the timebase interrupt when the TBIF bit becomes set. Reset clears the
TBIE bit.
1 = Timebase interrupt enabled
0 = Timebase interrupt disabled
TBON — Timebase Enabled
This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption
when its function is not necessary. The counter can be initialized by clearing and then setting this bit.
Reset clears the TBON bit.
1 = Timebase enabled
0 = Timebase disabled and the counter initialized to 0’s
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
153
FREESCALE [ Freescale ]
