Timebase Module (TBM)
TBON
÷ 2 ÷ 2 ÷ 2
÷ 2
÷ 2
÷ 16
÷ 2
÷ 32
÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2
÷ 64
OSCCLK
From OSC module
(See Chapter 5 Oscillator (OSC).)
÷ 8
÷ 2048
TBMINT
÷ 2 ÷ 2 ÷ 2 ÷ 2
÷ 2
÷ 2
÷ 2
÷ 32768 ÷ 65536 ÷ 131072
÷ 262144
TBIF
TBIE
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
SEL
Figure 10-1. Timebase Block Diagram
10.4 Timebase Register Description
The timebase has one register, the TBCR, which is used to enable the timebase interrupts and set the
rate.
Address:
$0051
Bit 7
6
TBR2
0
5
TBR1
0
4
TBR0
0
3
2
1
TBON
0
Bit 0
R
Read:
Write:
Reset:
TBIF
0
TACK
0
TBIE
0
0
0
= Unimplemented
R
= Reserved
Figure 10-2. Timebase Control Register (TBCR)
TBIF — Timebase Interrupt Flag
This read-only flag bit is set when the timebase counter has rolled over.
1 = Timebase interrupt pending
0 = Timebase interrupt not pending
MC68HC908AP Family Data Sheet, Rev. 4
152
Freescale Semiconductor
FREESCALE [ Freescale ]
