Chapter 10
Timebase Module (TBM)
10.1 Introduction
This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user
selectable rates using a counter clocked by the selected OSCCLK clock from the oscillator module. This
TBM version uses 18 divider stages, eight of which are user selectable.
10.2 Features
Features of the TBM module include:
•
Software programmable 8s, 4s, 2s, 1s, 2ms, 1ms, 0.5ms, and 0.25ms periodic interrupt using
32.768-kHz OSCCLK clock
•
User selectable oscillator clock source enable during stop mode to allow periodic wake-up from
stop
10.3 Functional Description
This module can generate a periodic interrupt by dividing the oscillator clock frequency, OSCCLK. The
counter is initialized to all 0s when TBON bit is cleared. The counter, shown in Figure 10-1, starts counting
when the TBON bit is set. When the counter overflows at the tap selected by TBR[2:0], the TBIF bit gets
set. If the TBIE bit is set, an interrupt request is sent to the CPU. The TBIF flag is cleared by writing a 1
to the TACK bit. The first time the TBIF flag is set after enabling the timebase module, the interrupt is
generated at approximately half of the overflow period. Subsequent events occur at the exact period.
The reference clock OSCCLK is derived from the oscillator module, see 5.2.2 TBM Reference Clock
Selection.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
151
FREESCALE [ Freescale ]
