Exception Control
7.5.2.1 Interrupt Status Register 1
Address:
$FE04
Bit 7
IF6
R
6
5
IF4
R
4
IF3
R
3
IF2
R
2
IF1
R
1
0
Bit 0
Read:
Write:
Reset:
IF5
0
R
0
R
R
0
0
0
0
0
0
0
R
= Reserved
Figure 7-12. Interrupt Status Register 1 (INT1)
IF6–IF1 — Interrupt Flags 6–1
These flags indicate the presence of interrupt requests from the sources shown in Table 7-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0 and Bit 1 — Always read 0
7.5.2.2 Interrupt Status Register 2
Address:
$FE05
Bit 7
IF14
R
6
5
IF12
R
4
IF11
R
3
IF10
R
2
IF9
R
1
IF8
R
Bit 0
IF7
R
Read:
Write:
Reset:
IF13
R
0
0
0
0
0
0
0
0
R
= Reserved
Figure 7-13. Interrupt Status Register 2 (INT2)
IF14–IF7 — Interrupt Flags 14–7
These flags indicate the presence of interrupt requests from the sources shown in Table 7-3.
1 = Interrupt request present
0 = No interrupt request present
7.5.2.3 Interrupt Status Register 3
Address:
$FE06
Bit 7
0
6
5
IF20
R
4
IF19
R
3
IF18
R
2
IF17
R
1
IF16
R
Bit 0
IF15
R
Read:
Write:
Reset:
IF21
R
R
0
0
0
0
0
0
0
0
R
= Reserved
Figure 7-14. Interrupt Status Register 3 (INT3)
IF21–IF15 — Interrupt Flags 21–15
These flags indicate the presence of an interrupt request from the source shown in Table 7-3.
1 = Interrupt request present
0 = No interrupt request present
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
107
FREESCALE [ Freescale ]
