SIM Registers
A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the SIM break status
register (SBSR).
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 7-18 shows stop mode entry timing.
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
CPUSTOP
IAB
IDB
STOP ADDR
STOP ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 7-18. Stop Mode Entry Timing
STOP RECOVERY PERIOD
ICLK
INT/BREAK
IAB
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
STOP +1
Figure 7-19. Stop Mode Recovery from Interrupt or Break
7.7 SIM Registers
The SIM has three memory-mapped registers:
•
•
•
SIM Break Status Register (SBSR) — $FE00
SIM Reset Status Register (SRSR) — $FE01
SIM Break Flag Control Register (SBFCR) — $FE03
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
111
FREESCALE [ Freescale ]
